Verification Engineer
모집부문 및 자격요건
| 담당업무 | 자격요건 | 인원 |
|---|---|---|
| Verification Engineer |
- BS or MS in EE with 3 years industry related experience in design & verification - Strong analysis skills required to debug RTL design problems - Understanding customer’s design and verification issues and provide formal solution - Knowledge and experiences of SV(System Verilog) and SVA(System Verilog Assertion) language - Knowledge and experiences on various AMBA(APB, AHB, AXI, ACE) protocols - Knowledge of simulation-based verification concepts such as scoreboard and functional coverage, etc. - Understanding customer’s design and verification issues and create test scenario in Testbench - Experience with UVM verification technology is a plus- Experience with Debugging about Low-power simulation - Automation skills using Perl scripting
|
1 명 |
근무조건
- 급여조건: 연봉 연봉범위
전형단계 및 제출서류
- 전형단계: 서류전형 > 면접진행 > 최종심사 > 최종합격
- 추가 제출서류
이력서, 자기소개서
접수방법
2021-09-08 (수) 23시59분까지
- 접수방법: 인크루트 채용시스템
- 접수양식: 인크루트 이력서
기타 유의사항
- 입사지원서 및 제출서류에 허위사실이 있을 경우 채용이 취소될 수 있습니다.
