(ÁÖ) µð¿¡À̾ÆÀÌ¿À SoC Verification ÆÀ¿ø ¸ðÁý
¸ðÁýºÎ¹® ¹× ÀÚ°Ý¿ä°Ç
[ASIC Verification ¾÷¹«]
- SoC IP ¹× Full chip
level °ËÁõ
- ½Ã¹Ä·¹ÀÌ¼Ç È¯°æ ±¸Ãà
[Çʼö»çÇ×]
- SoC Verification °æÇè
- Cadence ¹× Synopsys Tool »ç¿ë
- SystemVerilog/UVM »ç¿ë
- HDL/C »ç¿ë
- ½ÇÀå chip ºÐ¼®
- Test Equipment »ç¿ë
(Oscilloscope, Log Analyzer µî)
[¿ì´ë»çÇ×]
- ASIC/SoC ¼³°è °æÇè
- NAND/SD/eMMC/SATA/PCIe Verification °æÇè
- Computer Architecture ´ÉÅë
- SVA »ç¿ë °¡´É
- Script language(Perl/shell/tcl) »ç¿ë °¡´É
[ÀÚ°Ý¿ä°Ç]
- °æ·Â»çÇ×: ½ÅÀÔ, °æ·Â(¿¬Â÷¹«°ü)
- Çз»çÇ×: Çз¹«°ü
- Á÷¹«±â¼ú: ±â¼ú¿¬±¸¼Ò
±Ù¹«Á¶°Ç
ÀüÇü´Ü°è ¹× Á¦Ãâ¼·ù
Á¢¼ö¹æ¹ý
ä¿ë½Ã
±âŸ À¯ÀÇ»çÇ×