Cadence Design Systems

Design Engineer - AE ½ÅÀÔ»ç¿ø ¸ðÁý

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are seeking talented Application Engineers dedicated for physical design in Cadence Korea. You will be responsible for the physical 

design implementation projects.

 

         The candidate will perform the physical design implementation, including floor planning, power grid design, place and route, 

           clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.

         The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed designs at the

           latest technology nodes.

         The responsibility of the candidate includes participating in or leading next generation physical design, methodology and flow development.

         The candidate will work closely with RTL design team to ensure successful tapeouts.

 

Requirements

         BS/MS in EE/CS with 1+ years of hands-on experience in physical design and verification.

         Experienced with ASIC design flow, hierarchical physical design strategies, methodologies, and understand deep sub-micron technology 

          issues.

         Solid knowledge on Low Power Design, DFT, static timing analysis and closure, data skew balancing, duty cycle adjustment, 

           EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM and P&R.

         Able to assume responsibility for a variety of technical tasks and to work independently

         Able to be hands-on at all levels of design, with the ability to verify, test, and characterize own designs.

         Self-motivated, able to work as a team player, and good English communication skills.

 

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