[´ã´ç¾÷¹«] • IP design o ARM based SOC designÀ» À§ÇÑ IP configuration and generation. + ARM Corelink, AMBA designer, Socrates (ARM), Flexnoc (Arteris), coreConsultant (Synopsys) µî o CMU (Clock Management Unit), PMU (Power Management Unit), DFTMUX (Design For Test MUX) µî SOC level system IP ¼³°è. o UART, I2C, SPI, DMA µî peripheral IP ¼³°è o SystemVerilog ¹× UVM ±â¹ÝÀÇ VIP (Verification IP) ¸¦ ÀÌ¿ëÇÑ IP function °ËÁõ
• SOC block ¹× full chip integration o Architecture, power, clock Á¤º¸¸¦ ¹ÙÅÁÀ¸·Î energy efficient high performance SoC system ¼³°è o Image processing (acquisition/compression/display/understanding) subsystem ¼³°è o High speed IP (PCIe/Ethernet/USB/UFS/LPDDR µî)¸¦ link/phy subsystem integration. o IP-XACT ±â¹ÝÀÇ fullchip/block integration
• Synthesis ¹× timing constraint o Clock Á¤º¸¸¦ ÀÌ¿ëÇÑ SDC Á¦ÀÛ ¹× physical implementation Áö¿ø
[±Ù¹«ºÎ¼ ¹× Á÷±Þ/Á÷Ã¥] ±Ù¹«ºÎ¼: SOC HW °³¹ßÆÀ Á÷±Þ/Á÷Ã¥: ÆÀ¿ø
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[ÀÚ°Ý¿ä°Ç] °æ·Â»çÇ×: ½ÅÀÔ, °æ·Â(1³â ÀÌ»ó ) Çз»çÇ×: ´ëÇб³(4³â)Á¹¾÷ Á÷¹«±â¼ú: RTL, HW¼³°è ±âŸ: ÀÚ°Ý - SOC ¼³°è flow ¹× ¼³°è ¹æ¹ý·Ð¿¡ ´ëÇÑ ÀÌÇØ - Verilog, SystemVerilog¸¦ È°¿ëÇÑ RTL ³í¸®È¸·Î ¼³°è Áö½Ä - ¼³°è»ç¾çÀ» ÀÌÇØ ¹× °áÁ¤ÇÏ°í ȸ·Î·Î ±¸ÇöÇÒ ¼ö ÀÖ´Â ´É·Â
¿ì´ë Á¶°Ç - ISP Æ÷ÇÔ multimedia IP, CPU, CPU cache system, SOC bus, DRAM controller, NPU, GPU µî IP µé¿¡ ´ëÇÑ domain knowledge - ARM CPU spec ÀÌÇØ. ARM CPU subsystem ¼³°è °æÇè. - Low power ¼³°è °æÇè - Â÷·®¿ë EE hardware architecture ¹× integration ÇÁ·Î¼¼½º °æÇè - Â÷·®¿ë ECU System HW °³¹ß °æÇè
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