¸ðÁýºÎ¹® ¹× ÀÚ°Ý¿ä°Ç
´ã´ç¾÷¹« | ÀÚ°Ý¿ä°Ç | Àοø |
---|---|---|
- RTL Verification Engineer | - ÀüÀÚ/¹ÝµµÃ¼ °ü·Ã Çаú Çлç ÀÌ»ó - °æ·Â 3³â ~ 12³â - SoC µðÁöÅÐ ¼³°è ȤÀº °ËÁõ °æÇè - ´Ù¾çÇÑ IP RTL ¼³°è ȤÀº °ËÁõ °æÇè - ARM CPU »ç¿ë °æÇè / CPU Architecture ÀÌÇØ - AMBA BUS (APB, AHB, AXI, ACE) protocol °æÇè - Verilog HDL, SystemVerilog »ç¿ë °æÇè - Perl, Python µîÀÇ script »ç¿ë °æÇè - C, C++ »ç¿ë °æÇè - UVM °ËÁõ °ü·Ã °æ·ÂÀÚ ¿ì´ë (Çʼö ¾Æ´Ô) |
1 ¸í |
±Ù¹«Á¶°Ç
ÀüÇü´Ü°è ¹× Á¦Ãâ¼·ù
Á¢¼ö¹æ¹ý
ä¿ë½Ã
±âŸ À¯ÀÇ»çÇ×
00