- Solid experience in running physical-aware logic synthesis (DC-G or Genus) and achieving optimal synthesis QoR on high-performance and low power designs 
- Solid experience in developing power intent using UPF and running static low power verification tool like Synopsys VC-LP or
similar tools 
- Solid experience in running gate level power estimation using Synopsys PrimeTime-PX 
- Developing the timing constraints and running the full-chip logic synthesis 
- Collaborating with DSP to accomplish the design closure for tape-out 
- Block-level PPA analysis for marketing and sales/BD support 
- Samsung design methodology support for ASIC customers 
- Good understanding of chip floor plan to get the best PPA during physical-aware synthesis