"Video Technology Leader for Silicon HW IP"
Ĩ½º¾Ø¹Ìµð¾î´Â ¹ÝµµÃ¼ ¼³°èÀÚ»ê (Silicon IP) ±â¾÷À¸·Î, Video Codec IP¸¦ ¿¬±¸°³¹ßÇÏ´Â ºñµð¿À IP¿¡ Æ¯ÈµÈ Àü¹®È¸»ç ÀÔ´Ï´Ù. ÃÖ±Ù¿¡´Â Global Top tier °í°´À» ¿¬´Þ¾Æ È®º¸ÇÏ¸ç ¶Ç ÇѹøÀÇ ¼ºÀåÀ» ÀÌ·ç¾ú½À´Ï´Ù. ±Ù·ÎÀÚ 80%°¡·®ÀÌ °³¹ßÀÚÀ̸ç, ±Ù¹«Çϱâ ÁÁÀº ȯ°æÀ» À§ÇØ ²÷ÀÓ¾øÀÌ °í¹ÎÇÕ´Ï´Ù.
[¹ÝµµÃ¼IP °³¹ß»ç] RTL Design/Verification Engineer
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• °³¹ßÁßÀÎ HW IP¿¡ ´ëÇÑ °ËÁõ ȯ°æ setup ¹× debugging • ±â °³¹ßµÈ HW IPÀÇ ±â´É ¼³°è(RTL coding)¹× °ËÁõ(simulation and synthesis) ¹× À¯Áö º¸¼ö • °³¹ß ¿Ï·áµÈ Product¿¡ ´ëÇÑ Customer Áö¿ø |
[»ç¿ë±â¼ú] Java JavaFPGA FPGAPython PythonPerl PerlC CLinux LinuxVerilog Verilog [ÀÚ°Ý¿ä°Ç] • ÀüÀÚ(°øÇÐ)°ú Ãâ½Å(Çлç or ¼®»ç) • Verilog & C ±âº» Áö½Ä º¸À¯ [¿ì´ë»çÇ×]
• C/C++/Verilog HDL¿¡ ´ëÇÑ Áö½Ä º¸À¯ • Linux/Unix ȯ°æ¿¡ ´ëÇÑ Áö½Ä º¸À¯ • Python/Perl/JAVA/Shell Script¿¡ ´ëÇÑ Áö½Ä º¸À¯ • Video Codec¿¡ ´ëÇÑ Áö½Ä º¸À¯ • FPGA Development Environment °æÇè • Fluent in English |
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