S»ç ´ë±â¾÷

ȸ·Î¼³°è  Analog IP °³¹ß °æ·Â ä¿ë

¸ðÁýºÎ¹® ¹× ÀÚ°Ý¿ä°Ç

¸ðÁýºÎ¹® ´ã´ç¾÷¹« ÀÚ°Ý¿ä°Ç Àοø
Analog IP °³¹ß

[´ã´ç¾÷¹«]

¹ÝµµÃ¼ Analog IP °³¹ß

- HPC, AI, 5G, IoT, Automotive µî Â÷¼¼´ë Á¦Ç°Çâ Ãʹ̼¼ °øÁ¤ Analog IP ¼³°è
(High-Speed/High-Resolution Data Converter, Ultra-low jitter PLL, High-efficiency power IP,
High-Accuracy Sensor, Analog Front End)
- High Performance Computing À» À§ÇÑ Interface IP ¼³°è
- 5G/IoT Platform ¿¡ ÇÊ¿äÇÑ Sub-6GHz/mmWave ¿ë RF ȸ·Î °³¹ß
- ½Å °øÁ¤ ¼±Çà °³¹ß ¹× ºÐ¼®À» ÅëÇÑ Analog/RF Design Infra °³¹ß

[ÀÚ°Ý¿ä°Ç]

°æ·Â»çÇ×: °æ·Â(4³â ÀÌ»ó )
Çз»çÇ×: Àü±âÀüÀÚ : ÀüÀÚ±âÇÐ, ȸ·ÎÀÌ·Ð, ³í¸®¼³°è, ³í¸®È¸·Î, µðÁöÅÐ ÀüÀÚȸ·Î, ¾Æ³¯·Î±× ÁýÀûȸ·Î,

¹ÝµµÃ¼°øÇÐÀüÀÚ±âÇÐ, ÀüÀÚ±âÇÐ, ¹°¸®ÀüÀÚ, ½ÅÈ£ ¹× ½Ã½ºÅÛ, °øÇмöÇÐ,

µðÁöÅÐ ½Ã½ºÅÛ ¼³°è ¹× ½ÇÇè, µðÁöÅÐ ½Åȣó¸®ÀÇ ±âÃÊ, ¸ÖƼ¹Ìµð¾î °øÇа³·Ð, È®·ü ¹× ·£´ýÇÁ·Î¼¼½º µî

 Requirements Analog/Digital ȸ·Î¼³°è¸¦ ÀÌÇØÇÏ°í ºÐ¼® °¡´ÉÇÑ ÀÚ ÇÁ·Î±×·¡¹Ö ¾ð¾î (Verilog/C µî) ±¸Çö °¡´ÉÇÑ ÀÚ ¹ÝµµÃ¼ ¼³°è/ºÐ¼®À» À§ÇÑ EDA(Electronic Design Automation) ȯ°æ (Synopsys/ Mentor/ Cadence/ Ansys/ CST µî) ¿ª·® º¸À¯ÀÚ ¿øÀÎ ºÐ¼® ¹× ÇØ°á ´É·Â Pluses Á÷¹«¿Í ¿¬°üµÈ °æÇè º¸À¯ÀÚ (ÇÁ·ÎÁ§Æ®, ³í¹®, ƯÇã, °æÁø´ëȸ)


0 ¸í

±Ù¹«Á¶°Ç

  • °í¿ëÇüÅÂ: Á¤±ÔÁ÷
  • ±Þ¿©Á¶°Ç: ¿¬ºÀ ÇùÀÇ ÈÄ °áÁ¤

ÀüÇü´Ü°è ¹× Á¦Ãâ¼­·ù

  • ÀüÇü´Ü°è: ¼­·ùÀüÇü > ¸éÁ¢ÁøÇà > ÃÖÁ¾½É»ç > ÃÖÁ¾ÇÕ°Ý
  • Ãß°¡ Á¦Ãâ¼­·ù
    À̷¼­, ÀÚ±â¼Ò°³¼­

Á¢¼ö¹æ¹ý

ä¿ë½Ã

  • Á¢¼ö¹æ¹ý: ÀÎÅ©·çÆ® ä¿ë½Ã½ºÅÛ, À̸ÞÀÏ
  • Á¢¼ö¾ç½Ä: ÀÎÅ©·çÆ® À̷¼­, ÀÚÀ¯¾ç½Ä

±âŸ À¯ÀÇ»çÇ×

  • ÀÔ»çÁö¿ø¼­ ¹× Á¦Ãâ¼­·ù¿¡ ÇãÀ§»ç½ÇÀÌ ÀÖÀ» °æ¿ì ä¿ëÀÌ Ãë¼ÒµÉ ¼ö ÀÖ½À´Ï´Ù.

00