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  - DBÇÏÀÌÅØÀº DB±×·ì(ÏÁ µ¿ºÎ) °è¿­»ç·Î, 1997³â ¼³¸³µÈ ±¹³» ÃÖÃÊÀÇ ½Ã½ºÅ۹ݵµÃ¼ Àü¹®±â¾÷ÀÔ´Ï´Ù. 
  - Brand»ç¾÷ºÎ´Â ÀÚü±â¼ú·ÂÀ¸·Î LCD ¹× OLED¿ë Display ±¸µ¿Ä¨(DDI)À» ¼³°è, °ø±ÞÇÏ°í ÀÖ½À´Ï´Ù.
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LDDI ȸ·Î¼³°è
(Large Display

Driver IC)

[Analog design]
∙ Source Driver Design
 - DAC, Low Power High Speed OP-AMP
 - ADC Design
 - LDO, Regulator, OSC Design

[Logic design]
∙ ´ëÇü Display Á¦Ç° Mixed Logic Design
 - RTL Logic Design
 - Full Custom Logic Design

[Interface design]
∙ High Speed Interface Design (RX, TX)
 - PLL, DLL based CDR Design
 - Serial Interface Design (eDP, DP, HDMI)

¡Ø Analog/Logic/Interface °¢ ºÐ¾ßº° ä¿ë
[Çʼö]
∙ LDDIÁ¦Ç° IC¼³°è °æ·Â 3³â ÀÌ»ó (Interface: 5³â ÀÌ»ó)

[¿ì´ë]
∙ (°øÅë) LDDI¿ë Display(LCD/OLED) IC Á¦Ç° ¾ç»ê °æÇèÀÚ
∙ (Logic) RTL ¾ç»ê °æÇèÀÚ
∙ (Analog) Matlab ÀÌ¿ë Frequency domain Analysis °¡´ÉÀÚ
∙ (Interface) CTLE, DFE Design, Verilog A Design °æÇèÀÚ
ÆDZ³

MDDI ȸ·Î¼³°è
(Mobile Display

Driver IC) 

[Analog design]
∙ Power Design
 - LDO, Regulator, DC-DC µî
∙ Source Driver Design
 - DAC, Low Power High Speed OP-AMP µî

[Logic design]
∙ Mobile Display Driver IC
∙ RTL ¹× Verilog¸¦ ÀÌ¿ëÇÑ Digital Logic ¼³°è 
∙ High Speed Interface (MIPI)
∙ Memory Control (Flash/SRAM)
∙ Image Processing / Compression IP 
∙ System Verilog / UVM (Universal Verification Methodology) ȯ°æÀ» ÀÌ¿ëÇÑ Verification

[Verification design]
∙ System Verilog / C ¾ð¾î / Python
∙ UVM (Universal Verification Methodology) ȯ°æÀ» ÀÌ¿ëÇÑ Verification °æÇè
∙ Driver IC Spec ÀÌÇØ ¹× °ËÁõ Modeling °æÇè

¡Ø Analog/Logic/Verification °¢ ºÐ¾ßº° ä¿ë
[Çʼö]
∙ DDIÁ¦Ç° IC¼³°è °æ·Â 3³â ÀÌ»ó

[¿ì´ë]
∙ Mobile¿ë Display(LCD/OLED) IC Á¦Ç° ¾ç»ê °æÇèÀÚ
ÆDZ³
ÀÀ¿ë±â¼ú
(Display
Driver
IC)
∙ Display Driver IC Àü±âÀû/±¤ÇÐÀû Ư¼º Æò°¡
 - OLED Mobile ¿ë DIC (Tcon Embeded DIC)
 - LCD/OLED TV ¿ë DIC
∙ °í°´ ±â¼úÀû ¿ä±¸ »çÇ× ´ëÀÀ (°í°´»çÀÌÆ®)
 - IC ºÒ·® ºÐ¼® ¹× Trouble Shooting
 - ±¸µ¿ ÃÖÀû Á¶°Ç Tuning
[Çʼö]
∙ DIC ±¸µ¿ Æò°¡ °ü·Ã ¾÷¹« °æ·Â 3³â ÀÌ»ó

[¿ì´ë]
∙ LCD/OLED Display Module ȸ·Î °³¹ß °æÇèÀÚ
∙ ºñÁî´Ï½º ¼öÁØÀÇ Áß±¹¾î ±¸»çÀÚ
∙ PCB ȸ·Î¼³°è ¿ª·® º¸À¯ÀÚ (PADS Logic µî)
∙ Python, System Verilog ¿î¿ë °¡´ÉÀÚ
ÆDZ³
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