✏️ ¸ðºô¸°Æ®ÀÇ SoC Design Engineer´Â SoC ¾ÆÅ°ÅØÃ³ ¹× ¹ö½º ±¸Á¶¸¦ ¼³°èÇϰí Ĩ »ý»ê Àü¹Ý¿¡ °ü¿©ÇÏ´Â AI ¹ÝµµÃ¼ °³¹ßÀÇ ÇÙ½ÉÀ̶ó ÇÒ ¼ö ÀÖ½À´Ï´Ù.
FPGA¿Í ASIC °³¹ßÀÇ Àü °úÁ¤À» Á÷Á¢ °æÇèÇÏ°í ½ÍÀ¸½Å ºÐ, µðÁöÅРȸ·Î ¼³°è ºÐ¾ßÀÇ Àü¹®¼ºÀ» °ÈÇϸ鼵µ ´Ù¾çÇÑ ¿£Áö´Ï¾î¿Í ¼ÒÅëÇϸç TÀÚÇü ÀÎÀç·Î ¼ºÀåÇÏ°í ½ÍÀ¸½Å ºÐ, Â÷¼¼´ë ±¹°¡Àü·«±â¼úÀÎ AI ¹ÝµµÃ¼¿¡ °ü½ÉÀÌ ¸¹À¸½Å ºÐ, ±×¸®°í »õ·Î¿î µµÀüÀ» Áñ±â½Ã´Â ºÐµé²² Àû±Ø Ãßõµå¸³´Ï´Ù!
Job Responsibilities
- RTL ¼³°è ¹× °ËÁõ (Top, Block, IP level)
- Interface, Power management, Clocking µîÀ» À§ÇÑ RTL °³¹ß
- ´Ù¾çÇÑ ·¹º§ÀÇ IP/SoC µðÀÚÀο¡ ´ëÇÑ Verification
Requirements
- ÀüÀÚ°øÇÐ Çлç ÀÌ»ó ÇÐÀ§ ¼ÒÀ¯ÀÚ
- Standard HDLs(Verilog, SystemVerilog µî) Ȱ¿ëÀÌ ´É¼÷ÇϽŠºÐ
- SoC ¹× Bus Architecture¿¡ ´ëÇÑ ÀÌÇØµµ°¡ ³ôÀ¸½Å ºÐ
- RTL design ¹× °ËÁõ ¹æ¹ý·Ð¿¡ ´ëÇÑ ÀÌÇØµµ°¡ ³ôÀ¸½Å ºÐ
- ½ºÅ©¸³Æ® ¾ð¾î(Python, Tcl, Perl µî) Ȱ¿ëÀÌ ´É¼÷ÇϽŠºÐ
Preferred Qualifications
- 3³â ÀÌ»óÀÇ RTL design ¶Ç´Â RTL verification °æ·ÂÀÌ ÀÖÀ¸½Å ºÐ
- SoC ¼³°è ¹× »ý»ê Àü¹Ý¿¡ ´ëÇÑ °æÇèÀÌ ÀÖÀ¸½Å ºÐ
- ÇÁ·Î±×·¡¹Ö ¾ð¾î(C/C++, JAVA µî) Ȱ¿ëÀÌ ´É¼÷ÇϽŠºÐ
- High speed interface¿¡ ´ëÇÑ °æÇèÀÌ ÀÖÀ¸½Å ºÐ
- FPGA ¶Ç´Â ASIC °³¹ß °æÇèÀÌ ÀÖÀ¸½Å ºÐ
- µðÀÚÀÎÇϿ콺, RTL ¼³°èȸ»ç °æ·ÂÀÌ ÀÖÀ¸½Å ºÐ
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