[´ë±â¾÷°è¿­»ç] RTL Verification Engineer

[´ë±â¾÷°è¿­»ç] RTL Verification Engineer

[´ë±â¾÷°è¿­»ç] RTL Verification Engineer

[´ë±â¾÷°è¿­»ç] RTL Verification Engineer

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¸ðÁýºÎ¹® ´ã´ç¾÷¹« ÀÚ°Ý¿ä°Ç Àοø
RTL verification engineer

SoC °ËÁõ 

ÀüÀÚ/¹ÝµµÃ¼ °ü·Ã Àü°ø

- SoC µðÁöÅÐ ¼³°è ȤÀº °ËÁõ °æÇè (3³â~18³â)
- ´Ù¾çÇÑ IP RTL ¼³°è È¤Àº °ËÁõ °æÇè
- ARM CPU »ç¿ë °æÇè / CPU Architecture ÀÌÇØ
- AMBA BUS (APB, AHB, AXI, ACE) protocol °æÇè
- Verilog HDL, SystemVerilog »ç¿ë °æÇè
- Perl, Python µîÀÇ script »ç¿ë °æÇè
- C, C++ »ç¿ë °æÇè
- UVM °ËÁõ °ü·Ã °æ·Â ¿ì´ë


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