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Architecture ÆÀÀº »õ·Î¿î NPU ¹× System Architecture¸¦ Á¤ÀÇÇÏ°í, ´Ù¾çÇÑ ½Å°æ¸Á¿¡ ´ëÇÑ ¼º´É/Àü·Â/¸éÀû ¹× À¯¿¬¼ºÀ» °³¼±Çϱâ À§ÇÑ Çõ½ÅÀûÀÎ Á¢±Ù ¹æ½ÄÀ¸·Î Architecture¸¦ ÃÖÀûÈ­ÇÏ´Â ÀÏÀ» ´ã´çÇÕ´Ï´Ù.

- ±âÁ¸ ¹× »õ·Ó°Ô ºÎ»óÇÏ´Â ´Ù¾çÇÑ ½Å°æ¸ÁÀ» Ž»öÇÏ°í ºÐ¼®ÇÏ¿© ¾ÆÀ̵ð¾î¸¦ µµÃâ
- ¾ÆÀ̵ð¾îÀÇ Å¸´ç¼ºÀ» Æò°¡ÇÏ°í °íµµÈ­
- ¸¶ÀÌÅ©·Î ¾ÆÅ°ÅØó, RTL, ½Ã¹Ä·¹ÀÌÅÍ, ÄÄÆÄÀÏ·¯ µî NPUÀÇ ´Ù¾çÇÑ ¿µ¿ª¿¡ ´ëÇÑ °æÇè
- NPU System Architecture - SoC, SiP, Memory subsystem, NoC and etc.  
- System ¹× Server level communication through UCIe, PCIe, Ethernet and etc.
- Server ¹× Cloud level security
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[Çʿ俪·® ¹× Á÷¹«°æÇè]
- NPU or System ¾ÆÅ°ÅØÃÄ ¹× ¸¶ÀÌÅ©·Î ¾ÆÅ°ÅØÃÄ ¼öÁØÀÇ Çϵå¿þ¾î ¼³°è °æÇè
- ¼º´É/Àü·Â/¸éÀû ÃÖÀûÈ­ °æÇè
- C/C++/Python ÇÁ·Î±×·¡¹Ö
- SoC, SiP °æÇè
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- ÃÑ °æ·Â : ÃÑ 3³â ÀÌ»ó (À¯°ü°æ·Â 2³â ÀÌ»ó)
- ÇзÂ/Àü°ø : ¼®»çÀÌ»ó / ÄÄÇ»ÅÍ ¹× ÀüÀÚ°øÇР
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- Many-core/Multi-chip NPU/GPU/Microprocessor °³¹ß °æÇè
- Architecture exploration tool °³¹ß °æÇè
- Hardware simulator °³¹ß °æÇè
- RTL ¼³°è °æÇè
- ML framework °æÇè (Tensorflow, PyTorch, TVM)
- ½Å°æ¸Á ¸ðµ¨ °æ·®È­/ÃÖÀûÈ­ °æÇè
- Compiler °ü·Ã °æÇè
- Firmware °ü·Ã °æÇè
- SiP, UCIe, PCIe, °ü·Ã °æÇè
- Server Security °ü·Ã °æÇè
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