Introduction to BOS Semiconductors  

BOS Semiconductors was launched with the vision of “Leading mobility innovation with semiconductor technology” mainly targeting autonomous driving SOC, HPC, and Gateway SOC in the automotive domain. We aim to provide a total solution that includes the design of semiconductors and related software. We have secured seed round funding from Hyundai Motors and additional rounds from various investors are scheduled. All current members are from top global companies with extensive semiconductor, software, business and legal experience. HQ is located in Pangyo, Korea, and an Engineering R&D Center is located in Ho Chi Minh City, Vietnam.  

About BOS HW team   

Our mission is to design all types of automotive SoC including SoCs with high performing computing engines used in AD/ADAS, infotainment and gateway as well as SoCs applied in areas that require high reliability such as engine, battery management system, powertrain and brake control system ECUs. We perform the design and verification of LSIs with gate counts of multi-billion gates based on architecture that is best-suited for automotive functional safety and security. BOS's HW team is fully responsible for the production-readiness and reliability of our developed chips and conducts thorough silicon validation tasks through in-depth DFT and evaluation board. By having experts in design and verification work together in a systematic and collaborative manner, we aim to participate in global projects to fulfill the needs of our global customer base.

Main Responsibilities

IP / Subsystem Design and Fullchip Integration

I. Full chip SoC Design

- Fullchip and subblock integration based on IP-XACT methodology

- Fullchip level front-end job including Lint, CDC, Formality, SDC script

- Bus architecture and system architecture design / System analysis

II. IP and Subsystem Design

- High speed interface including PCIe, MIPI CSI / DSI, USB, Ethernet

- Processor subsystem including CPU, GPU, NPU, DSP, Debugger, Interrupt controller, MMU, Cache, Bus interconnect

- System IP design including Clock, Power and OTP controllers and system monitors