- 8+ years¡¯ experience in digital logic design verification.
- Deep knowledge of SystemVerilog and UVM.
- Experience defining detailed verification plans for SoC top-level verification.
- Experience implementing UVM testbenches for SoC top-level verification.
- Experience developing UVM-based test-benches.
- Strong communication skills are a must, as the candidate will interface with many different groups within the company.