- 8+ years’ experience in digital logic design verification.

 - Deep knowledge of SystemVerilog and UVM.

 - Experience defining detailed verification plans for SoC top-level verification.

 - Experience implementing UVM testbenches for SoC top-level verification.

 - Experience developing UVM-based test-benches.

 - Strong communication skills are a must, as the candidate will interface with many different groups within the company.

 - 총 보유경력 : 8년이상

 - 학력/전공 : 학사이상

 - Experience in formal verification

 - Experience with emulators

 - Experience in design verification modeling (C++, SystemC)

 - Experience in SoC security testing and familiarity with security protocols and data protection mechanisms.

 - Experience with SoC booting processes and validation of boot loaders.

 - Proficiency in measuring and optimizing SoC performance metrics.