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Job Description | 1. DFT flow (DT-DFT) - DFT Implementation - SCAN insertion / ATPG / Scan Simulation (Test Compiler / TetraMax) - BIST/BIRA Insertion & Simulation : Tessent MBIST / JTAG / IJTAG - Advanced DFT : 3D-IC, ISO26262, scan dump - Hierarchical DFT Flow - TOP DFT Architecture Design - ATE Vector setup - Yield improve - SDC Creation & Clean - Spyglass LINT/SDC/DFT Check - Logic Synthesis : DC/DCT/DCG - Equivalence Check : Formality/Conformal - STA (Static Timing Analysis) - Simulator & Debugger : VCS / NC-verilog / Verdi *Experience in Tcl/Tk, PERL, Makefile is a Plus
2. PV flow (DT-PV) - 5+ years of complete hands-on experience in Physical Verification. - Also well versed with Top PV closure for Samsung foundry. - Should have some PD background as well so that he/she can guide the PD engine - Should possess excellent debug and problem solving skills - Need to have understanding of PV methodologies so as to understand, setup an edit the PV setup if and when required. - These are the checks that they must be proficient in > DRC > LVS > PERC > ERC > VRC (DFM) > PM (DFM) > LFD (DFM) > CMP (DFM) > MAS (DFM) - Technologies: 28nm and below. * Experience in Tcl/Tk, PERL, Makefile is a Plus | |
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