* 회사소개 : 반도체 설계 및 검증 솔루션 유명 외국계기업
* Position : SOC Engineer (대리 ~ 과장급)
* Location : 용인시 기흥
* Job Description and Requirements :
Job Description :
· Responsible for Synthesis and Timing Closure at Block/Sub system or SoC level.
· Responsible for performing the input/output deliverable sanity check (Constraints analysis, LDRC,
LEC, Low-Power) at the RTL/Netlist-level to enable smooth timing closure.
· Work closely with RTL design, DFT and Physical Implementation teams to meet timing closure goals.
· Play a key role in understanding the design goals to meet performance/timing requirements,
understand the clocking architecture and thier relationship and lead timing related discussions
at the Block/Sub-system or SoC level.
Requirements :
· Experience in performing multi-mode/multi-corner timing closure of complex blocks/sub-systems
or SoC from synthesis to timing-signoff.
· Experience with timing constraints (SDC) development and validation at block/sub-system level
for various modes.
· Ability to debug, analyze and provide solution to timing closure challenges at block/sub-system level.
· Ability to automate or write scripts using TCL, Perl or Python.
· Understanding of Low-power concepts (UPF) and experience in performing low-power checks
at the RTL/Netlist level.
· Experience in performing Logical Equivalence Checks (formal verification).
· Experience with Synopsys SDC, Fusion Compiler, Primetime tools.
· Bachelors or Master’s degree with 5+ years of experience in IC-Design/Semiconductor Engineering
or related field
【 접수기간 및 방법】
- 접수 기간 : ASAP
- 접수방법 : 온라인 또는 e-mail
→ ******@*******.*** / ******@*******.***
- 담당자 : 박현준 이사
***-****-**** / ***-****-****
【 제출서류 】- 영문 이력서