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[Job title]

Digital design engineer

 

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[Responsibilities]

- Design, implement, and debug complex logic designs

- Integrate your IP into a bigger and more complex IP

- Support all front-end integration activities like Lint, CDC, Synthesis, and ECO

- Implement design automation via Python or other languages

- Work with other specialists that are members of the SOC Design, SOC Design Verification, Emulation, STA, and Physical Design teams

- Collaborate with software and systems teams to ensure a high-quality system

[Qualifications & Skills]

- Expertise in RTL and/or testbench development using Verilog/SystemVerilog.

- Experience with digital ASIC/SOC design flow from RTL to silicon characterization.

- Ability to understand project specifications and come up with a comprehensive set of requirements and develop verification test-plans

- Experience debugging RTL designs using an HDL simulator

- Familiar with code base management method including subversion, git, GitHub, etc.

- Familiar with Synopsys and Cadence EDA tools for Simulation, Synthesis, Timing (STA), Formal and Assertion based verification, etc.

- Excellent communication skills both verbal and written for documentation and reporting

- Fluent English language 

[Education and Experience]

- BS (or higher degree) in Electrical Engineering or related disciplines

- Experience Required: 3+ Years (no requirement for new college graduate)

 

 

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