Display ÆÐ³Î Test ÀåºñÁ¦Á¶»ç(±èõ)
HW °³¹ß(¼±ÀÓ~Ã¥ÀÓ) °æ·Âä¿ë
¸ðÁýºÎ¹® ¹× ÀÚ°Ý¿ä°Ç
¸ðÁýºÎ¹® | ´ã´ç¾÷¹« | ÀÚ°Ý¿ä°Ç | Àοø |
---|---|---|---|
Display ÆÐ³Î test ÀåºñÁ¦Á¶(±èõ) HW °³¹ß(¼±ÀÓ~Ã¥ÀÓ) |
[´ã´ç¾÷¹«] - µð½ºÇ÷¹ÀÌ ÆÐ³Î Å×½ºÆ® Àåºñ °ü·Ã FPGA º¸µå ȸ·Î ¼³°è
- °ü·Ã °í¼Ó ½ÅÈ£ º¸µå ȸ·Î ¼³°è [±Ù¹«ºÎ¼ ¹× Á÷±Þ/Á÷Ã¥]
Á÷±Þ/Á÷Ã¥: ¼±ÀÓ~Ã¥ÀÓ |
[ÀÚ°Ý¿ä°Ç] 4³âÁ¦ ÇлçÀÌ»ó °æ·Â 5~15³â °æ·ÂÀÚ ¿ì´ë»çÇ× - µð½ºÇ÷¹ÀÌ, ¹ÝµµÃ¼Å×½ºÆ®, Ä«¸Þ¶ó¸ðµâ Å×½ºÆ® µî °æ·ÂÀÚ
- FPGA(Xilinx, Altera), DDR4 Memory Çϵå¿þ¾î ¼³°è °æÇèÀÚ
- High Speed (Displayport, MIPI C/D-PHY) ½ÅÈ£ ȸ·Î ¼³°è °æÇèÀÚ |
0 ¸í |
±Ù¹«Á¶°Ç
ÀüÇü´Ü°è ¹× Á¦Ãâ¼·ù
Á¢¼ö¹æ¹ý
2025-10-31(±Ý) 23½Ã59ºÐ±îÁö
±âŸ À¯ÀÇ»çÇ×
00