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[´ã´ç¾÷¹«] * ¾Æ·¡ Æ÷Áö¼Ç Áß¿¡¼ º»ÀÎÀÇ ¾÷¹«°æ·ÂÀ» °í·ÁÇϼż ¼±Åà Áö¿øÇÏ½Ã¸é µË´Ï´Ù.
1. Digital Design (verification) [´ã´ç¾÷¹«] - Top integration / Top regression test ȯ°æ ±¸Ãà - IP º° regression Å×½ºÆ® ȯ°æ ±¸Ãà - FPGA / ZEBU °ËÁõ ¹× ÇÊ¿ä °ËÁõ IP °³¹ß [Áö¿øÀÚ°Ý] - Àü°ø : ÀüÀÚ/Àü±â/ÄÄÇ»ÅͰøÇÐ - °æ·Â : 4³â ÀÌ»ó [¿ì´ë»çÇ×] - UVM, ZEBU, FPGA °ü·Ã °æÇè ¹× Áö½Ä º¸À¯ - ºñµð¿À ½Ã½ºÅÛ °³¹ß °ËÁõ °æÇè º¸À¯
2. Digital Design (DDR PHY/ Controller ¼³°è) [´ã´ç¾÷¹«] LPDDR 4/5 PHY / Controller °³¹ß ¨Õ PHY -Digital PHY RTL ¼³°è -Timing Constraint ÀÛ¼º -Physical Implementation Guide ¹× Áö¿ø ¨è Controller -LPDDR4 memory controller ±â¹ÝÀ¸·Î LPDDR5 memory controller °³¹ß -Timing Constraint ÀÛ¼º -Physical Implementation Guide ¹× Áö¿ø [Áö¿øÀÚ°Ý] - Àü°ø : ÀüÀÚ/Àü±â°øÇÐ - °æ·Â : 4³â ÀÌ»ó [¿ì´ë»çÇ×] - DDR PHY, Controller ¼³°è ¹× ¾ç»ê °ü·Ã °æÇè ¹× Áö½Ä º¸À¯
3. Digital Design (AXI Bus ¼³°è) [´ã´ç¾÷¹«] - APB, AHB, AXI Master / Slave / Async bridge IP ¼³°è - Bus rate control IP, Arbiter ¼³°è - DDR°ú ¿¬°èÇÏ¿© Bus Æ©´×, ÃÖ´ë BWÈ®´ë - ½Å±Ô LPDDR4/5¿¬°èÇÏ¿© Bus backbone ¼³°è [Áö¿øÀÚ°Ý] - Àü°ø : ÀüÀÚ/Àü±â°øÇÐ - °æ·Â : 4³â ÀÌ»ó [¿ì´ë»çÇ×] - ARM CPU, Bus °ü·Ã °æÇè ¹× Áö½Ä º¸À¯
4 Digital Design (CPU/MCU) [´ã´ç¾÷¹«] - ARM CPU/MCU ±×¸®°í RISC-V °³¹ß °æÇè êó - ÀÚ»ç T-Con °³¹ß °úÁ¦¿¡ ¸ÂÃç MCU Platform °³¹ß ¹× °ü·Ã Peri ¼³°è - SoC °³¹ß ½Ã Target PPA ¸¸Á·À» À§ÇÑ Core¿Í Configuration ¼±Á¤ - RTL, SDC ¹× Power Intent ÀÛ¼º°ú °ËÁõ - °¢Á¾ Benchmark¸¦ ÅëÇÑ ¼º´É Æò°¡ - Physical Implementation ´Ü°èº° °ËÁõ°ú multi-core power °ü¸® [Áö¿øÀÚ°Ý] - Àü°ø : ÀüÀÚ/Àü±â°øÇÐ - °æ·Â : 4³â ÀÌ»ó [¿ì´ë»çÇ×] - SoC ¾ç»ê °³¹ß °æ·Â
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[ÀÚ°Ý¿ä°Ç] °æ·Â: °æ·Â 4³â¡è ÇзÂ: ´ëÁ¹ ÀÌ»ó Á÷¹«±â¼ú: ȸ·Î¼³°è, ¹ÝµµÃ¼µð½ºÇ÷¹ÀÌ, ¹ÝµµÃ¼¼³°è, ¹ÝµµÃ¼Àåºñ, Àü±âÀüÀڹݵµÃ¼
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