Display Test ÀåºñÁ¦Á¶(±èõ)
FPGA FW engineer(¼±ÀÓ~¼ö¼®) °æ·Âä¿ë
¸ðÁýºÎ¹® ¹× ÀÚ°Ý¿ä°Ç
| ¸ðÁýºÎ¹® | ´ã´ç¾÷¹« | ÀÚ°Ý¿ä°Ç | Àοø |
|---|---|---|---|
Display ÆÐ³Î test ÀåºñÁ¦Á¶(±èõ) FPGA FW engineer (¼±ÀÓ~¼ö¼®) |
[´ã´ç¾÷¹«] - µð½ºÇ÷¹ÀÌ ÆÐ³Î Å×½ºÆ® Àåºñ ¹× FPGA º¸µå °³¹ß (´ç»ç´Â LGD Çù·Â ¾÷üÀÓ) - µð½ºÇ÷¹ÀÌ ÆÐ³Î Å×½ºÆ®¸¦ À§ÇÑ ÆÐÅÏ Á¦³Ê·¹ÀÌÅÍÀÇ FPGA RTL ¹× Æß¿þ¾î °³¹ß - FPGA RTL ÄÚµù ¼³°è (Verilog/VHDL) [±Ù¹«ºÎ¼ ¹× Á÷±Þ/Á÷Ã¥]
Á÷±Þ/Á÷Ã¥: ÁÖÀÓ~Ã¥ÀÓ |
[ÀÚ°Ý¿ä°Ç] 2³âÁ¦ Àü¹®ÇлçÀÌ»ó, °æ·Â 5~25³â °æ·ÂÀÚ ¿ì´ë»çÇ× - Xilinx FPGA »ç¿ë°æÇèÀÚ (DDR3.4, AXI bus, VDMA µî) - Xilinx Microblaze, ZYNQ µî À¯»ç MCU »ç¿ë °æÇèÀÚ - µð½ºÇ÷¹ÀÌ ÀÎÅÍÆäÀ̽º ¹× µðÁöÅÐ ¿µ»óó¸® °æÇèÀÚ (MIPI, RGB, LVDS,
Displayport µî) |
0 ¸í |
±Ù¹«Á¶°Ç
ÀüÇü´Ü°è ¹× Á¦Ãâ¼·ù
Á¢¼ö¹æ¹ý
±âŸ À¯ÀÇ»çÇ×
00