À¯ÇÑȸ»ç ¾ÆÀÌ¿¡½º¿¡½º¾ÆÀÌÄÚ¸®¾Æ

(¿Ü±¹°è ±â¾÷) Memory ȸ·Î ¼³°è ¿¬±¸¿ø ¸ðÁý

¸ðÁýºÎ¹® ¹× ÀÚ°Ý¿ä°Ç

¸ðÁýºÎ¹® ´ã´ç¾÷¹« ÀÚ°Ý¿ä°Ç Àοø
Memory ȸ·Î ¼³°è ¿¬±¸¿ø

[´ã´ç¾÷¹«]

Digital design expert.
Can use Verilog tool for simulation or RTL code design.
Ability to analyze design error on silicon level.
Floor-planning of memory architecture.
Design and simulation of memory decoding, read/write control circuits at block-level and full-chip level.

[ÀÚ°Ý¿ä°Ç]

°æ·Â: ½ÅÀÔ/°æ·Â 5~15³â
ÇзÂ: ´ëÁ¹ ÀÌ»ó
Á÷¹«±â¼ú: CAD


2 ¸í

±Ù¹«Á¶°Ç

  • °í¿ëÇüÅÂ: Á¤±ÔÁ÷(¼ö½À±â°£3°³¿ù)
  • ±Þ¿©Á¶°Ç: ¿¬ºÀ ÁÖ40½Ã°£, 4200~12000¸¸¿ø

ÀüÇü´Ü°è ¹× Á¦Ãâ¼­·ù

  • ÀüÇü´Ü°è: ¼­·ùÀüÇü > ¸éÁ¢ÁøÇà > ÃÖÁ¾½É»ç > ÃÖÁ¾ÇÕ°Ý
  • Ãß°¡ Á¦Ãâ¼­·ù
    À̷¼­, ÀÚ±â¼Ò°³¼­

Á¢¼ö¹æ¹ý

  • Á¢¼ö¹æ¹ý: ÀÎÅ©·çÆ® Á¢¼ö
  • Á¢¼ö¾ç½Ä: ÀÎÅ©·çÆ® À̷¼­

±âŸ À¯ÀÇ»çÇ×

  • ÀÔ»çÁö¿ø¼­ ¹× Á¦Ãâ¼­·ù¿¡ ÇãÀ§»ç½ÇÀÌ ÀÖÀ» °æ¿ì ä¿ëÀÌ Ãë¼ÒµÉ ¼ö ÀÖ½À´Ï´Ù.

00