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Digital Design
Serdes Architect (Link)

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Digital Design
Serdes Architect (Link)

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- Digital ȸ·Î ¼³°è (ASIC / FPGA)
: High Speed Interface ¹× SerDes Digital IP ȸ·Î ¼³°è ¹× °ËÁõ (¿¹ : eDP, MIPI, Vx1, CEDS µî)
: Digital IP ¼³°è (DSC, FEC, HDCP µî)
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: FPGA IP (GTY, SerDes, FPLL µî) Ȱ¿ëÇÑ °í¼Ó Interface ȸ·Î ¼³°è
- MCU Bus Architecture ¹× Peripheral IP ¼³°è

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